1. Field of the Invention
The subject invention pertains to a process for the production of semiconductor wafers having a heteroepitaxial SiGe layer on the front side, and having reduced amounts of threading dislocations, cross hatch, and misfit dislocations, while also offering reduced bow, warp, and improved global and local flatness.
2. Background Art
A crystalline heteroepitaxial layer of SiGe deposited on a silicon single crystal substrate by epitaxial deposition typically differs from the substrate in several material properties including crystal lattice dimensions and thermal expansion coefficient. SiGe deposition on Si is a well known system to increase the lattice constant from Si to pure Ge which has a lattice constant being 4.2% larger than that of Si. Hereinafter, SiGe is an abbreviation of Si(1-x)Gex, wherein x represents a value in the range of from 0.2 to 1.0. During the early stages of the deposition the heteroepitaxial SiGe layer is strained with respect to the underlying substrate lattice. After exceeding a certain layer thickness (critical thickness) the crystal of the heteroepitaxial layer starts to relax via the insertion of so called misfit dislocations (MFD). Although oriented in the plane perpendicular to the growth direction not all MFD extend to the edge of the substrate wafer but a certain number bend and form threading dislocations (TD) propagating through the growing layer to the surface. TD forming clusters along lines are called pile ups (PU) and are especially harmful for electronic devices. The stress fields from the dislocation network also cause a surface roughening called cross-hatch. The formation of MFD, PU, TD, cross-hatch and a bending of the wafer (bow, warp) are mechanisms by which the strain from the lattice mismatch is relieved. Many epitaxial deposition techniques have been developed to reduce the negative effects of the strain relaxation on the crystal quality of the heteroepitaxial layer. Grading of the Ge concentration in the SiGe layer has been a successful way to reduce the density of TD and PU and the surface roughness of so-called SiGe buffer layers. Many variations of grading the Ge concentration to match the crystal lattice of Si to the intended crystal lattice constant at the surface of the graded SiGe buffer layer have been developed. For example, the concentration of Ge in the SiGe buffer layer is graded continuously or in steps.
So far little attention has been given to the reactions after the deposition has ended. Typically the deposition is done by heating a silicon single crystal substrate wafer to a certain temperature and then providing the components for growing a film in the gas phase (e.g. CVD, PVD, MBE). When the film growth ends the film is fully or partially relaxed with regard to the substrate. Sometimes annealing steps are applied to fully relax the SiGe buffer. After the deposition is completed the cooling of the layered wafer starts. Because of the difference in thermal expansion coefficient between heteroepitaxial layer and substrate new stress is generated. The stress components effect the layer properties in a similar way as stress introduced by lattice mismatch during film growth. Secondary relaxation, bowing of the wafer and roughening of the surface are the mechanisms to release this stress.
Attempts have been made to reduce the bowing of the wafer. Such attempts have been successful to a certain extent by providing thin intermediate layers of strained Si in the heteroepitaxial layer. An approach of this kind is disclosed in US2008/0017952 A1, another one in US2009/0087961 A1.
According to US2003/0033974 A1 a flat epitaxial wafer having III-V nitride layers without defects and micro cracks may be obtained by depositing such layers on the front and the back side of a substrate.
These methods have all been used to compensate the bowing of the wafer caused by the stress generated by a heteroepitaxial front side layer. The present invention intends to provide a method which uses the stress generated by a backside layer to change the growth and cooling mechanism of the heteroepitaxial front side layer and thereby improving the crystal quality of the front side layer, especially the TDD and surface roughness caused by cross-hatch generation.
The provision of the stress compensating layer prevents a degradation of the heteroepitaxial layer during the phase after cooling down the wafer from the deposition temperature. After the deposition, the heteroepitaxial layer is in a fully or partially relaxed state depending on the conditions during deposition. When the film forming gases are turned off, the wafer is usually cooled down in a controlled manner. Due to the thermal mismatch of the substrate and the heteroepitaxial layer, new stress is generated and causes a set of secondary relaxation processes. These include the formation of secondary dislocations, roughening of the surface and also bowing of the wafer. Typically a strong increase in the density of TD and the surface roughness towards the wafer edge would be observed. However, depositing a stress compensating layer providing the desired amount of stress on the back side of the substrate before depositing the heteroepitaxial layer counteracts the generation of new stress, eliminates the center to edge non-uniformity in terms of RMS-roughness, reduces the density of TD and the roughness caused by cross-hatch and improves the bow of the wafer.
However, although the deposition of a stress compensating layer prior to the deposition of the heteroepitaxial layer on the front side solves the issues regarding defects of the heteroepitaxial layer and bowing of the wafer, other wafer parameters can suffer significantly. Most important for the fabrication of advanced CMOS transistors for sub-45 nm device generations are parameters related to the geometry of the wafer especially global and local flatness parameters (SFQR, SBIR) and nanotopography.
The process flow for producing a heteroepitaxial 300 mm wafer suitable for 32 nm device generation and below needs to be improved to fulfill the tight specifications regarding these parameters despite adding the stress compensating layer on the backside and the heteroepitaxial layers on the front side of a wafer.